10 Things to Review Prior to Release to a Fabricator
By Mark Thompson | Published on April 5, 2010 - 10:00 AM PST
Hello all. In this month’s "Engineering Spotlight" I will go over 10 things that should be reviewed prior to releasing a PCB to be fabricated. I want to stress that depending upon the application some of these things may not be feasible in a given design.
Clarify copper weight intentions:
Clarify the copper weight intentions on a drawing or read me file. Note that most Fabricators plate up in whole ounce increments to meet the IPC mandate of a minimum of 8/10ths of a mil in the barrel for continuity. So, half ounce starting outer layers would finish at 1.5 ounce or 2.1 mils. Inner layer copper weights should be expressed as a finished copper weight as typically inner layers do not receive an additional plate up.( exceptions would be blind or buried layers) . Also remember fabricators will typically associate an “etch compensation” based on the known loss from the etcher. A fairly typical rule of thumb is that for every half ounce of starting copper weight a half mil etch comp is performed on the artwork prior to etch.
Example of a potential problem callout:
Half ounce starting outer layer foil with .0035 spaces PRIOR to etch compensation. This would result in .003 mil spaces prior to process and this may cause some companies to either suggest starting on lighter copper such as Quarter ounce foil (at which point most fabricators do not even impose an etch Compensation) or “no Bid” the job.
Finished hole size vs. annular rings:
Also, as a recap from previous columns, remember a fabricator typically drills .004-.005 over the specified FINISHED hole size to plate down to the correct FINISHED size. This means the pads for signal layers should be at least .009-.010 over the F.H.S. ( .004-.005 for plate down and .002 per side annular ring prior to plate. For internal plane layers, the clearance or relief size should be approximately .015 over F.H.S. ( .004-.005 for plate down and a min of .005 per side from the edge of the drilled plated hole to adjacent copper pour. Typical tolerances for plated holes are +/-.003 and for Non plated holes +/-.002.
Via In Pad type structures:
If Via-InÐpad type structures exist on the design and one side is cleared of solder-mask and the other "Tented" or covered for the same hole, Solution entrapment can cause Black or oxidized holes. To avoid this, 80% of the barrel size can be cleared on the "tented" side to allow solution to flow freely through the hole, or better yet, for this type of application it is recommended the holes in question be filled after plate with either a conductive material or non-conductive epoxy. The surface is then "planarized" (Made flat) at this point it does not matter if one side of the via-in-pad is tented and the other cleared.
Utilizing .003 traces and .003 spaces:
Only use .003/.003 where necessary due to device pitch constraints. Fan out to a larger width outside the tight pitch areas whenever possible.
4101/ material callouts on drawings or "read me" notes:
Many times customers will list a number of different "families" of materials on a drawing as acceptable. This sometimes results in a call from your fabricator for clarification.
Example:
The callout on the drawing says, "material should be 4101/24 or 4101/26" this makes sense to a fabricator as they are both from the same "family" of materials (Both are E-glass and both have a Tg from 150-200c). Frequently we see callouts for multiple Families of materials for the same part. This is where a fabricator should clarify.
Example:
The callout note on the drawing says, "material should be 4101/26 or 4101/40" These 2 are from different "families" of materials. The /26 being E-glass and a Tg of approx 150-200, the /40 is a POLYIMIDE type material with a Tg of approx 260c.
Internal copper weights vs. dielectrics:
It is important to remember to calculate for the additional copper between dielectric sub sections on multilayer boards. Failure to consider the additional thicknessÕ of the internal copper weights sometimes results in sub sections too thin to accommodate both the desired Internal copper weight and the overall thickness requirements.
Board Stack-up Symmetry:
When at all possible maintain stack-up symmetry for the sake of board bow and twist. Here is an example of a board with high potential for warpage or bow and twist concerns. 6 layer board with Top layer being predominantly metal, layer 2 ground plane (also mostly metal) then power (also mostly metal) then a signal layer, another signal layer and finally the back side as pads only or signal layer, having basically three metal sections together and three signals or pads only layers together is a set up for board warp. Two examples of a symmetrical stack-up for a 6 layer board:
1. Top Layer 2. Top Layer Layer 2 - Plane Layer 2 - Signal Layer 3 - Signal Layer 3 - Plane Layer 4 - Signal (Or even a split plane) Layer 4 - Plane Layer 5 - Plane Layer 5 - Signal Bottom Layer Bottom Layer Blind or Buried Via jobs:
Save yourself some cost and time by setting up blind vias whenever possible through cores and avoid either sequential lamination or Controlled depth drilling scenarios when possible. Controlled depth drilled holes have difficulty getting solution in and out of fine holes and sequential lamination adds additional process steps that you pay for.
Unwanted or Unintentional Coupling:
Many times at layout the engineer may come back to the layout person and ask to pour copper externally wherever he can to create as much of a shield or "can" if you will from electrical emissions. Many times surface Impedance lines are not re-considered when this happens and by pouring copper too close to an Impedance controlled trace co-planar coupling may be induced resulting in either a change in line size or dielectric to achieve the desired impedances. A good rule of thumb is the "3x" rule; keep the copper pout at least 3 x the intended trace width away from the trace to avoid any unwanted co-planar coupling.
Consult your Fabricator:
Consult your fabricator or fabricators prior to trace layout for Impedance jobs when possible. Let them assist you in establishing dielectrics and lines sizes to get you to within 10% of the desired impedance(s). This way the job can go to almost any Fabricator and you should not get a call asking for large deviations in either line size or dielectric.
Finally, as an addendum to last month's "Keep them on the Inside" article about Keeping Impedance Signals on Internal layers...
Understand this is Dependant on Application and I would like to add that keeping impedance signals on internal layers is generally a good idea but at higher edge rates (40-50 GIG) Surface differential pairs can take a larger impedance hit than those placed Internally.
Thank you for your time.
Please feel free to call me with any questions or comments at:
(425) 823-7000 extension 239
or E-Mail me at MarkT@Prototron.com