Impedance Control: Calling Out Dielectric Just a Start
By Mark Thompson | Published on May 5, 2011 - 10:00 AM PST
In this month's column, I will elaborate on a point I have made many times in previous columns: The practice of trying to control impedances by merely calling out a material family and the dielectric distance between layers.
Here at Prototron, most of us have about 25 years of experience. So when we see a job with no callout for any controlled impedances, the preview and CAM folks with any experience will recognize things like serpentine traces for timing or differential pairs. Even the layer stack-up itself can scream signal control.
As I have said on many occasions in the "Bare (Board) Truth," merely calling out specific dielectrics between layers MAY NOT keep you within your desired impedance tolerance. If your tolerance is 20 to 30% (highly unlikely) and you have done your homework well, you will probably be fine no matter what fabricator you choose. However, if you require 5 to 10% control and you are not sharing impedance information with the fabricator, deviations in effective Dk of each sub-section, press parameters and environmental conditions can contribute to taking you out of tolerance.
Allow me to break this down further.
1. Effective Dk of Sub-Sections
The most common error: Assuming a single number for the Dk for all sub-sections throughout a multilayer board.
Why? Let's use high-temp FR-406 as an example. Cured cores of FR-406 types generally have an effective Dk range between 4.2 and 4.6 depending on the make-up and thickness of the core, whereas B-stage (pre-preg) is much lower in Dk--anywhere from 3.3 to 4. The thinner the pre preg or B-stage, the higher the resin content, and the higher the resin content, the lower the effective Dk.
Raw glass = somewhere around 6.0 Dk
Pure resin = somewhere around 2.5-3 Dk
Therefore, the effective Dk for all pregs and core materials are a combination of these two materials.
If you are pre-modeling impedances at 4.3 thinking you will be safe and the reality of the b-stage interface is closer to 3.3 this mis-match can mean the difference in tolerance and result in impedance mis-matches.
2. Press Parameters
Different press parameters such as temperature, heat rise, cycle time duration and pressure can also contribute to mismatches of predicted dielectrics resulting in Impedance variances.
3. Environmental Conditions
The least of the three, but environmental conditions are nonetheless contributing factors. You can get slight variances between fabricators depending upon the their location, the time of year and the companies' controls.
For example, our Tucson, Arizona facility is in an area that's predominantly hot, with little or no humidity. But at our shop in Redmond, Washington the opposite holds true; it's rainy with cooler temperatures and more humidity. Both shops offer the same products, but each must have unique, specific process controls to ensure the same results.
Fortunately, most fabricators now use a field solver impedance calculator with a "goal seek" function, such as Polar Instruments SI-8000 or SI-9000. This allows the fabricator to predict the impact of issues such as overplate, underplate, overetch, underetch, too much mask , too little mask, etc. This gives the fabricator the optimum line size (with the least amount of deviation from original size) to be able to deal with the 30 or so processes that make up PCB fabrication.
On the other hand, I have known many engineers and physicists over the years who claim that impedance control in general is a farce. They cite examples such as line lengths of less than 0.5" cannot really even be controlled.
Over the years we have had numerous customers insist that a certain layer in the stack-up is not a reference plane. From a fabricator's standpoint, ANY metal on either side above or below an intended impedance signal is a ref plane. One example would be a layer that is predominantly a signal layer in nature, with numerous routes and a small patch of metal residing above or below an impedance-controlled trace. The end-user may not technically consider this layer to be a ref plane because the majority of the layer is composed of routes, not plane.
The Bottom Line
If you really want to minimize costly revisions and time-to-market and ensure that your board is impedance controlled, tell the fabricator the following four things:
- The size of traces to be controlled. If ALL the traces of one size are not being controlled, consider calling out the specific traces by differentiating by 1/1000 of a mil. Fabricators cannot resolve this small a feature, but can select the impedance traces vs. non-impedance traces in case slight line size or space tweaks are necessary. For example, copper pour and other non-impedance controlled routes could be 0.0051" while the impedance tracks could be .005".
- The layers the traces reside on.
- The threshold to be achieved (50 ohms , 90 ohms , 100 ohms, etc.)
- The tolerance associated (+/-5%, 10%, 15%, etc.)
You need not specify the ref planes. The fabricator should query the specific impedance traces to be able to determine the ref planes for each scenario.
Thank you for your time.
Please feel free to call me with any questions or comments at:
(425) 823-7000 extension 239
or E-Mail me at MarkT@Prototron.com