Engineering Spotlight: Basic Impedance Fabrication Guidelines | Part 2
By Mark Thompson | Published on October 22, 2009 - 10:00 AM PST
In this column I will talk more about Co-planar structures and unique reference plane scenarios as they relate to PCB fabrication. In the first part, I will talk about Co-planar type structures and the effect of un-intentional co-planar coupling on Impedances. In the second part, I will talk about the use of unique reference plane scenarios for multiple impedance’s. What benefits they may have vs. any drawbacks.
What is a “Co-Planar” structure?
Co-planarity, as it relates to the signal on a PCB is where a portion of metal plane exists on the same layer as the Impedance signal and induces some specific amount of coupling due to the proximity of the adjacent plane/copper pour. Often in conjunction with ref planes on adjacent layers these structures offer mechanical and heat sink capabilities greater than those in “free space” or in the case of the PCB, un-used non metal areas.
On the other hand, multiple sequential co-planar structures increase the possibility of cross talk and other un-wanted resonance effects, resulting in reduced Transmission line performance. An example of Unintentional co-planar coupling is when a design is near completion and all details about the outer layer Impedances have been worked out. At the last moment the Engineer asks for more Thermal dispersion or heat sink capabilities and asks the layout person to perform a copper pour on the Surface layers to create better thermal capacity and to minimize emissions. Having done so, the fabricator now attempts to model the impedances based on Co-planar Structures. In some cases, if the Impedances are not re-visited after final layout prior to release to the potential fabricator to within 10% of the original intended impedance, you may receive a call from your fabricator regarding subtle re-line sizing to get closer to the intended impedances.
Fig-1 (Click Image to see Larger Version)
Fig-2 (Click Image to see Larger Version)
For many years the “3x rule” has been used and is still valid for most applications today. This is where no copper pour gets any closer to an Impedance controlled trace than three times its width. An example would be a .005 line with at least .015 ground separations. (Distance to adjacent copper pour) would be consider un-coupled, anything less may induce a slight amount of coupling changing the Impedance results up to 5%. In a +/-10% environment this is a problem for a fabricator.
What do you do? , As always I advocate involving the fabricator at the earliest possible time possible before trace layout begins on tight tolerance impedance jobs. Your chosen fabricator should ask at that time whether or not you have any copper pour on any layer closer than 3 x the controlled trace width. Also remember any copper pour added should have the same set – back distance (distance to adjacent copper pour).
Impedance Tolerances today are getting tighter requiring greater process controls to be able to achieve the Customer’s desired impedances. In addition, some new materials force fabricators to make larger and larger trace and space adjustments to deal with the sometimes large deviation in the available dielectrics on these new Material’s adding in more process variables. Most outer layer impedances today are already at minimum dielectric distances to the ref plane to keep the line and space sizes down for real estate purposes. Add into this close ground coupling and sometimes the necessary modifications result in trace or space values BEYOND the capability of the Fabricator.
Dual or triple role Reference planes...
As a fabricator, often we see Customers using different reference planes for signals that exist on the same layer. An example of this would be some traces such as surface timing traces may reference the next underlying layer in the stack up as a ground layer; these traces may be fairly small. In other sections of the same outer layer a larger trace may reference a plane buried somewhere deeper in the stack up such as a layer 3. The obvious benefit of this being un-used board real estate on internal signal layers can now have small patches of ground ref plane added to achieve multiple Impedances.
How is this done?
In the case of the Larger trace or traces if set up for differential pairs for certain devices the ground layer 2 has a “pass through“ section below the intended impedance traces on the surface to allow the metal on layer 3 (or some other plane or signal plane layer buried deep in the stack up to act as reference plane for the surface feature.) Remembering that the further dielectric distance from the ground reference plane to the surface trace the wider the surface trace needs to be. Many times we see customers take this to an extreme and have all layers referencing all other layers in a jumble of multiply used reference planes. This can again be set up for cross talk and other resonance issues if the part placement and proximities are not carefully calculated by the Engineer prior to trace layout.
Broadside Impedance structures...
A Broadside coupled Impedance structure is one where the signal or signals reference one another in the PCB Z axis between two reference planes, unlike a “dual strip-line” type structure where the two signal layers are routed 90 degrees to one another to minimize the cross section of trace coupling here, the traces are DIRECTLY above and below one another to INTENTIONALLY couple. The stack up for these type structures must place the two signals on either side of a single core to minimize any trace offset. If placed on two separate cores, any registration movement in lamination could create an un-wanted trace offset resulting in irregular coupling. If as mentioned before the two signals reside on either side of a single cured core, the movement layer to layer would be minimal through the lamination process.
Thank you for your time.
Please feel free to call me with any questions or comments at:
(425) 823-7000 extension 239
or E-Mail me at MarkT@Prototron.com

